1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device having adjustable length and number of pages.
2. Description of the Related Art
In a typical semiconductor memory device, when an internal memory cell array block is accessed, the number of bits in a row address and the number of bits in a column address are fixed. Further, since the numbers of bits in the row address and the column address respectively determine the number of pages (also referred to as the page depth) and page length of the device, and the typical semiconductor device has a fixed number of pages and a fixed page length. However, recent multimedia technology requires a semiconductor memory device having an adjustable number of pages and an adjustable page lengths.
FIG. 1 is a block diagram showing the architecture of a conventional 1 Megabit (Mb) DRAM. In the DRAM, the row address is 9 bits RA0 to RA8, the column address is 9 bits CA0 to CA8, and the data bus is 4 bits wide.
Referring to FIG. 1, the DRAM includes a memory block 101, a sense amplifying and write driving block 103, four input buffers I10 to I13, four output multiplexers M10 to M13, and four output buffers O10 to O13. Memory block 101 has eight memory cell array blocks 10 to 17, eight local row decoders R10 to R17 and a column decoder C10. Sense amplifying and write driving block 103 includes ten sense amplifiers S10 to S19.
A ninth bit RA8 of a row address that was input from outside of the DRAM selects either memory cell array blocks 10, 12, 14, and 16 or memory cell array blocks 11, 13, 15 and 17. Eight row address bits RA0 to RA7 select a wordline (not shown) of each of memory cell array blocks 10 to 17. For example, when ninth bit RA8 of the row address is low, that is, an inverted bit RA8B is high, memory cell array blocks 10, 12, 14 and 16 are selected. When ninth bit RA8 of the row address is high, memory cell array blocks 11, 13, 15 and 17 are selected. The number of wordlines, i.e., the number of pages in each of memory cell array blocks 10 to 17 is 256.
Column lines (not shown) of each of memory cell array blocks 10 to 17 are selected by bits CA0 to CA7 of the column address that was input from outside of the DRAM. The ninth column address bit controls sense amplifiers S10 to S19 and the write drivers W10 to W19. Accordingly, the number of columns in each of memory cell array blocks 10 to 17 is 256. When both ninth bit RA8 of the row address and ninth bit CA8 of the column address are low, memory cell array blocks 10 and 14 are selected for access. When ninth bit RA8 of the row address is low, and ninth bit CA8 of the column address is high, memory cell array blocks 12 and 16 are selected for access. When ninth bit RA8 of the row address is high, and ninth bit CA8 of the column address is low, memory cell array blocks 11 and 15 are selected for access. When both ninth bit RA8 of the row address and ninth bit CA8 of the column address are high, memory cell array blocks 13 and 17 are selected for access.
In the DRAM of FIG. 1, a single data access accesses two memory cell array blocks 10 and 14, 11 and 15, 12 and 16, or 13 and 17. A page includes four rows of memory cells, one row from each of four memory cell array blocks 10 to 13 or 14 to 17. Thus, the page length is twice the number of column in a single memory cell array block or 512, and the number of pages is twice the number of rows in a single memory cell array block.
FIGS. 2A and 2B are block diagrams of sense amplifiers S10 to S13 and S16 to S19 and write drivers W10 to W13 and W16 to W19 of FIG. 1. In FIGS. 2A and 2B, signal POISE is a sense amplifier enable signal, IOi and IOiB are an input/output line and a complementary input/output line, DOi and DOiB are a data output line and a complementary data output line, signal PDT is a write driver enable signal, and line DIi is a data input line.
FIGS. 3A and 3B are respectively block diagrams of a sense amplifier and a write driver unit such as sense amplifiers S14 and S15 and write drivers W14 and W15, which are at the edges of sense amplifying and write driving block 103. In FIGS. 3A and 3B, signal PBLSi is a block select signal, and signals POISE, CA8 and PDT, and lines IOi, IOiB, DOi, DOiB and DIi are described above.
FIG. 4 is a block diagram of a block controller which generates block select signal PBLSi from row address bit RA8.
As described above, in the conventional semiconductor memory device, the number of pages and the page length are fixed. Thus, the conventional semiconductor memory device cannot adjust the number or length of pages for a memory access operation.
In accordance with an embodiment of the present invention, a paged memory device includes a page control circuit for generating a control signal that varies the number and length of pages in response to a page control signal. The control signal controls a sense amplifying and write driving circuit for multiple memory cell array blocks. The page control circuit controls a row address and a column address to generate the control signal, that is, varies the number and the length of pages. In response to the control signal, the sense amplifying and write driving circuit senses, amplifies, and outputs data from a memory cell array block selected from among the memory cell array blocks, and writes data into a memory cell array block selected from among the memory cell array blocks.
Preferably, the page control circuit may include an address buffer, a block controller and a control signal generator. The address buffer buffers the most significant bit (MSB) of the row address and outputs the buffered result, or ignores the MSB of the row address depending on the page control signal. The block controller generates a block select signal in response to the MSB and the next most significant bit of the row address, and the page control signal controls whether the control signal generator selects the MSB of the column address and or the block select signal as the control signal.